Operational amplifier circuit, sample/hold circuit and filter circuit using the operational amplifier circuit

ABSTRACT

An operational amplifier circuit is constituted by first and second inverted amplifier circuits (A 1 , A 2 ) that receive first and second input signals, a third inverted amplifier circuit (A 3 ) that receives an estimated common-mode output signal and an output signal from the first inverted amplifier circuit and outputs first and second output signals, a fourth inverted amplifier circuit (A 4 ) that receives the estimated common-mode output signal and an output signal from the second inverted amplifier circuit and outputs third and fourth output signals, where the estimated common-mode output signal is generated by adding the second output signal and the fourth output signal, and first and second non-inverted amplifier circuits (A 5 , A 6 ) that receive the estimated common-mode output signal and feed it back to the first and second inverted amplifier circuits.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a divisional of application Ser. No. 10/811,908, filed on Mar.30, 2004, which claims the benefit of priority to Japanese PatentApplication No. 2003-093575, filed on Mar. 31, 2003, all of which areincorporated herein by reference in their entireties.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to an operational amplifier circuit having a lowpower-supply voltage for handling differential signals, and morespecifically to an operational amplifier circuit capable of improvingfrequency characteristics and decreasing a common-mode signal, and asample/hold circuit and a filter circuit using the operational amplifiercircuit.

2. Description of the Related Art

The progress of integrated circuits is remarkable and the finefabrication process of integrated circuits progresses year by year.Although the finer fabrication process improves the performance oftransistors per se, a breakdown voltage of a transistor is gettinglower. Thus, the applicable power-supply voltage is getting lower. Whenthe power-supply voltage is low, the amplitude of voltage signals inintegrated circuits decreases, which makes it difficult to achieve adesired signal-to-noise ratio (S/N ratio). In order to solve thisproblem, a single-ended signal, which has been used, is changed to adifferential signal to thereby double the signal amplitude as comparedwith the single-ended signal amplitude.

In a balanced operational amplifier circuit, which handles differentialinput/differential output, however, it is necessary to suppress acommon-mode signal. If the elimination of the common-mode signal of theoperational amplifier circuit is insufficient, the voltage range of theoutput decreases, which causes a distorted differential signal.Especially at a low power-supply voltage, since the available voltagerange is limited, the suppression of a common-mode signal is essential.

Conventionally, in order to eliminate a common-mode signal, acommon-mode feedback circuit was used (see, e.g., Japanese PatentDisclosure KOKAI P2000-148262). The design of this common-mode feedbackcircuit is complicated as compared with a differential-input circuit ofa single-ended output, and defects such as oscillation tend to occur.

A balanced-type amplifier circuit was proposed in which amplifiercircuits having a plurality of input terminals and output terminals arecombined to decrease common-mode signal components (see, e.g., U.S.application Ser. No. 10/281,103 filed on Oct. 28, 2002).

Since the aforementioned conventional amplifier circuit can be realizedby a simple structure in which inverted amplifier circuits are combined,a low power-supply voltage can be realized. However, in cases where suchan amplifier circuit is constituted by two high gain stages in order toobtain enough gain, since the polarity must be reversed, it is necessaryto use low gain stages whose gain is approximately 1. Accordingly, thenumber of internal nodes from the input to the output becomes 2 (two).As the number of internal nodes increases, the frequency characteristicdeteriorates due to the parasitic capacitance in each node.

It is an object of the present invention to provide an operationalamplifier circuit of a balanced structure using two gain stagesappropriate for a low power-supply voltage, and in particular anoperational amplifier circuit with sufficient common-mode rejectionratio and with a frequency characteristic improved by limiting thenumber of internal nodes in the differential signal path to 1(one), anda sample/hold circuit and a filter circuit using the operationalamplifier circuit.

BRIEF SUMMARY OF THE INVENTION

According to an aspect of the invention, an operational amplifiercircuit is provided, the circuit comprising: a first inverted amplifiercircuit that receives a first input signal; a second inverted amplifiercircuit that receives a second input signal; a third inverted amplifiercircuit that receives an estimated common-mode output signal and anoutput signal of said first inverted amplifier circuit and outputs afirst output signal and a second output signal; a fourth invertedamplifier circuit that receives the estimated common-mode output signaland an output signal of said second inverted amplifier circuit andoutputs a third output signal and a fourth output signal; a firstnon-inverted amplifier circuit that receives the estimated common-modeoutput signal and outputs an output signal, the output signal of thefirst non-inverted amplifier circuit fed back to the output signal ofthe first inverted amplifier circuit; and a second non-invertedamplifier circuit that receives the estimated common-mode output signaland outputs an output signal, the output signal of the secondnon-inverted amplifier circuit fed back to the output signal of thesecond inverted amplifier circuit, wherein adding the second outputsignal and the fourth output signal creates the estimated common-modeoutput signal.

With an operational amplifier circuit of the present invention, inaddition to the suppression of a common-mode signal by the third andfourth inverted amplifier circuits, the common-mode signal can befurther suppressed by feeding the estimated common-mode output signalsback to outputs of the first and second inverted amplifier circuits viafirst and second non-inverted amplifier circuits. Furthermore, since thenumber of internal nodes in the differential signal path can be reducedto one, the frequency characteristic of the operational amplifiercircuit can also be improved.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a circuit diagram of an operational amplifier circuitaccording to a first embodiment of the present invention.

FIG. 2 is an equivalent circuit of the amplifier circuit shown in FIG. 1for the common-mode signals.

FIG. 3 is a circuit diagram of the inverted amplifier circuit with twoinputs and two outputs shown in FIG. 1.

FIG. 4 is a circuit diagram of an operational amplifier circuitaccording to a modification of the first embodiment.

FIG. 5 is an explanatory drawing for explaining the operation of theoperational amplifier circuit shown in FIG. 4.

FIG. 6 is a circuit diagram of an operational amplifier circuitaccording to a second embodiment.

FIG. 7 is a circuit diagram of an operational amplifier circuitaccording to a modification of the second embodiment.

FIG. 8 is a circuit diagram of an operational amplifier circuitaccording to a third embodiment.

FIG. 9 is a circuit diagram of an inverted amplifier circuit with twoinputs and two outputs shown in FIG. 8.

FIG. 10 is a circuit diagram of an operational amplifier circuitaccording to a modification of the third embodiment.

FIG. 11 is a circuit diagram of an operational amplifier circuit inwhich both the first embodiment and the third embodiment are employed.

FIG. 12 is a concrete circuit diagram of an operational amplifiercircuit shown in FIG. 11.

FIG. 13 is a circuit diagram showing a sampling state of a sample/holdcircuit using an operational amplifier circuit of the present invention.

FIG. 14 is a circuit diagram showing a holding state of a sample/holdcircuit using an operational amplifier circuit of the present invention.

FIG. 15 is a circuit diagram showing a filter using integrators.

FIG. 16 is a concrete circuit diagram of an integrator.

FIG. 17 is a circuit diagram of a transistor circuit of an invertedamplifier.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, embodiments according to the present invention will beexplained with reference to the attached drawings. Although thefollowing explanation will be directed to embodiments using field-effecttransistors, bipolar transistors also can be utilized.

First Embodiment

FIG. 1 shows an operational amplifier circuit of a balanced structureaccording to a first embodiment of the present invention.

This balanced operational amplifier circuit provides a first invertedamplifier circuit A1 with a (+) input terminal that receives a firstinput signal IN1 and a second inverted amplifier circuit A2 with a (+)input terminal that receives a second input signal IN2. This balancedoperational amplifier also provides a third inverted amplifier circuitA3 and a fourth inverted amplifier circuit A4. A (−) output terminal ofthe first inverted amplifier circuit A1 is connected to a first (+)input terminal of the third inverted amplifier circuit A3. A (−) outputterminal of the second inverted amplifier circuit A2 is connected to afirst (+) input terminal of the fourth inverted amplifier circuit A4. Afirst (−) output terminal of the third inverted amplifier circuit A3 isconnected to a first output terminal OUT1. A first (−) output terminalof the fourth inverted amplifier circuit A4 is connected to a secondoutput terminal OUT2. Second (+) input terminals and second (−) outputterminals of the third and fourth inverted amplifier circuits A3 and A4are connected with each other.

This balanced operational amplifier also provides non-inverted amplifiercircuits A5 and A6. The second (+) input terminals and the second (−)output terminals of the third and fourth inverted amplifier circuits A3and A4 are further connected to (+) input terminals of the non-invertedamplifier circuits A5 and A6. A (+) output terminal of the non-invertedamplifier circuits A5 is connected to the (−) output terminal of thefirst inverted amplifier circuit A1. A (+) output terminal of thenon-inverted amplifier circuit A6 is connected to the (−) outputterminals of the second inverted amplifier circuit A2.

In the aforementioned structure, when first and second input signals IN1and IN2 are inputted to the first and second inverted amplifier circuitsA1 and A2, the first and second inverted amplifiers A1 and A2 outputsignals Vo1 and Vo2, respectively. The output signal Vo1 of the firstinverted amplifier circuit A1 is inputted to the first (+) inputterminals of the third inverted amplifier circuit A3, and an estimatedcommon-mode output signal Voc is inputted to the second (+) inputterminals of the third inverted amplifier circuit A3. Consequently, thethird inverted amplifier circuit A3 outputs a first output signal(−(αVoc+βVo1), wherein α and β are positive constant numbers,respectively) to the first output terminal OUT1. The third invertedamplifier circuit A3 also outputs a second output signal (−γ(αVoc+βVo1),wherein α, β and γ are positive constant numbers, respectively).

Similarly, the output signal Vo2 of the second inverted amplifiercircuit A2 and the estimated common-mode output signal Voc are inputtedto the first and second (+) input terminals of the fourth invertedamplifier circuit A4, respectively. The fourth inverted amplifiercircuit A4 outputs a third output signal (−(αVoc+βVo2)) to the secondoutput terminal OUT2 and also outputs a fourth output signal(−γ(αVoc+βVo2), wherein α, β and γ are positive constant numbers,respectively).

The estimated common-mode output signal Voc is inputted to thenon-inverted amplifier circuits A5 and A6. The non-inverted amplifiercircuits A5 and A6 feed their output signals back to the output signalsof the first and second inverted amplifier circuits A1 and A2,respectively. The estimated common-mode output signal Voc is generatedby adding together the second output signal and the fourth outputsignal.

In the aforementioned operational amplifier circuit, when thecommon-mode voltage is fed back to the inverted amplifier circuits A3and A4 and this common-mode voltage increases, the non-invertedamplifier circuits A5 and A6 try to increase the output voltages Vo1 andVo2, respectively. To the contrary, the inverted amplifier circuits A3and A4 try to decrease the output voltages, respectively. As a result,negative feedback is formed. Therefore, different from the conventionalcircuit, a low-gain amplifier circuit for adding and inverting polarityis no longer required, and only one internal node is required.Therefore, improvement in speed can be realized.

Inverted amplifiers Aa1 to Aa4 as shown in FIG. 3 constitute each of theinverted amplifier circuits A3 and A4 shown in FIG. 1, for example. The(+) input terminals of the inverted amplifiers Aa1 and Aa2 are connectedwith each other, and input terminals of the inverted amplifiers Aa3 andAa4 are connected with each other. An output terminal of the invertedamplifier Aa1 is connected to an output terminal of the invertedamplifier Aa3, and an output terminal of the inverted amplifier Aa2 isconnected to an output terminal of the inverted amplifier Aa4.

Each of the inverted amplifiers Aa1 and Aa4 is constituted by the seriescircuit of PMOS transistor P1 and NMOS transistor N1 as shown in FIG.17, for example. In detail, a source of the PMOS transistor P1 isconnected to a power source Vdd, a gate of the PMOS P1 is connected to abias source Vbias, and a drain of the PMOS P1 is connected to a drain ofthe NMOS transistor N1 and an output terminal OUT(−). A source of theNMOS transistor N1 is grounded, and the gate is connected to an inputterminal IN(+). This circuit is simple in structure having no nodesother than the input terminal and the output terminal. In other words,the inverted amplifier circuits A3 and A4 have no internal node.

A gain for a differential signal path is represented by a product of thegains of the inverted amplifier circuits A1 (A2) and A3 (A4). In thisembodiment, the inverted amplifier circuits A1 and A2 have the samecharacteristic. Similarly, the inverted amplifier circuits A3 and A4 andthe non-inverted amplifier circuits A5 and A6 have the samecharacteristic, respectively. An equivalent circuit shown in FIG. 2 forthe common-mode signal can represent the operational amplifier circuitshown in FIG. 1. In this equivalent circuit, “gm1” denotes atransconductance of the inverted amplifier circuit A1; “gm3” denotes atransconductance of the inverted amplifier circuit A3 from one of theinputs of the inverted amplifier circuit A3 to the Voc output; “γ gm3”is a transconductance of the inverted amplifier circuit A3 from theother of the inputs of the inverted amplifier circuit A3 to the Vocoutput; “gm5” denotes a transconductance of the non-inverted amplifiercircuit A5; “ro1” denotes an output resistance of the inverted amplifiercircuit A1; “ro5” denotes an output resistance of the non-invertedamplifier circuit A5; and “ro3” and “ro4” denote output resistances ofthe inverted amplifier circuits A3 and A4 at the Voc output,respectively.

The transfer function from the input to the output can be obtained bythe following formula.Voc/IN=[gm1gm3(ro1/ro5)(ro3//ro4)]/[1+γgm3(ro3//ro4)+gm5gm3(ro1//ro5)(ro3//ro4)]

When γ≦1, gm5(ro1//ro5)>>1, in the embodiment, by the feedback using thenon-inverted amplifier circuits A5 and A6, the common-mode signal can bedecreased by approximately 1/[gm5(ro1//ro5)] as compared withconventional operational amplifier circuits.

Furthermore, as explained above, since the inverted amplifier circuitsA3 and A4 per se have no internal nodes, the number of internal nodes ofthe inverted amplifier circuit shown in FIG. 1 can be one in eachcircuit path of the differential signals. Therefore, the frequencycharacteristic can be improved.

FIG. 4 shows a modification of the operational amplifier circuit of thefirst embodiment. According to this modification, inverted amplifiercircuits A7 to A10 are added, while the first to sixth amplifiercircuits A1 to A6 are connected in the same manner as shown in FIG. 1.That is, the inverted amplifier circuit A7 is connected to the outputterminal of the first inverted amplifier circuit A1 and the invertedamplifier circuits A8 is connected to the output terminal of the secondinverted amplifier circuits A2. The inverted amplifier circuits A9 andA10 are disposed between the output terminals of the first and secondinverted amplifier circuits A1 and A2. The inverted amplifier circuitsA9 and A10 are connected with each other in parallel with reversepolarity.

In the other words, a (+) input terminal of the inverted amplifiercircuit A9 is connected to the (−) output terminal of the invertedamplifier circuit A1. A (−) output terminal of the inverted amplifiercircuit A9 is connected to the (−) output terminal of the invertedamplifier circuit A2. A (+) input terminal of the inverted amplifiercircuit A10 is connected to the (−) output terminal of the invertedamplifier circuit A2. A (−) output terminal of the inverted amplifiercircuit A10 is connected to the (−) output terminal of the invertedamplifier circuit A1. Input and output terminals of the invertedamplifier circuit A7 are connected to the (−) output terminal of theinverted amplifier circuit A1. Input and output terminals of theinverted amplifier circuit A8 are connected to the (−) output terminalof the inverted amplifier circuit A2.

According to the operational amplifier circuit having the aforementionedcircuit structure, with regard to differential input signals IN1 andIN2, a relationship between the output voltages of the invertedamplifier circuits A1 and A2 is represented by Vo1=·Vo2.

Accordingly, a signal component outputted from the inverted amplifiercircuit A9 is cancelled by a signal component outputted from theinverted amplifier circuit A8. Similarly, a signal component outputtedfrom the inverted amplifier circuit A10 is cancelled by a signalcomponent outputted from the inverted amplifier circuit A7. In otherwords, as shown in FIG. 5( b), the outputs of the inverted amplifiercircuits A7 to A10 do not contribute to the differential signals.

On the other hand, when input signals IN1 and IN2 are common-modesignals, a relationship between the output voltages of the invertedamplifier circuits A1 and A2 is represented by Vo1=Vo2.

In this case, a signal component outputted from the inverted amplifiercircuit A9 is added to a signal component outputted from the invertedamplifier circuit A8. Similarly, a signal component outputted from theinverted amplifier circuit A10 is added to a signal component outputtedfrom the inverted amplifier circuit A7. As a result, with regard tocommon-mode signals, the inverted amplifier circuits A7 to A10 arerepresented by the circuit structure shown in FIG. 5( a).

That is, resistance components at the outputs of the inverted amplifiercircuits A1 and A2 become very small, since a value of the resistancecomponent becomes proportional to an inverse of the transconductancefrom the inverted amplifier circuit A7 to the inverted amplifier circuitA10.

Accordingly, without increasing the number of internal nodes in eachcircuit path for the differential signals, a common-mode gain of theoutputs of the inverted amplifier circuits A1 and A2 can be furtherdecreased, which in turn can decrease a common-mode gain of the entireamplifier circuit.

Second Embodiment

FIG. 6 shows a balanced operational amplifier circuit according to asecond embodiment of the present invention. This operational amplifiercircuit provides a first inverted amplifier circuit A1 having a (+)input terminal that receives a first input signal IN1 and a secondinverted amplifier circuit A2 having a (+) input terminal that receivesa second input signal IN2.

This operational amplifier circuit also provides a third invertedamplifier circuit A3 and a fourth inverted amplifier circuit A4. A (−)output terminal of the first inverted amplifier circuit A1 is connectedto a first (+) input terminal of the third inverted amplifier circuitA3. A (−) output terminal of the second inverted amplifier circuit A2 isconnected to a first (+) input terminal of the fourth inverted amplifiercircuit A4. A first (−) output terminal of the third inverted amplifiercircuit A3 is connected to a first output terminal OUT1. A first (−)output terminal of the fourth inverted amplifier circuit A4 is connectedto a second output terminal OUT2.

Second (+) input terminals of the third and fourth inverted amplifiercircuits A3 and A4 are connected with each other, and second (−) outputterminals of the third and fourth inverted amplifier circuits A3 and A4are connected with each other. Therefore, the four terminals, i.e., thesecond (+) input terminals and the second (−) output terminals, areconnected together.

This operational amplifier circuit further provides non-invertedamplifier circuits A5 and A6. To (+) input terminals of the non-invertedamplifier circuits A5 and A6, a common-mode input signal Vic isinputted. A (+) output terminal of the non-inverted amplifier circuitsA5 is connected to the (−) output terminal of the first invertedamplifier circuit A1, and a (+) output terminal of the non-invertedamplifier circuits A6 is connected to the (−) output terminal of thesecond inverted amplifier circuit A2.

In the above structure, when first and second input signals IN1 and IN2are inputted to the first and second inverted amplifier circuits A1 andA2, respectively, the first and second inverted amplifier circuits A1and A2 output inverted output signals, respectively. Consequently, asignal proportional to the common-mode input signal Vic, which is anoutput signal of the non-inverted amplifier circuit A5, is added to theoutput signal of the inverted amplifier A1 and the sum of the outputsignals of A1 and A5, Vo1, is inputted to the first (+) input terminalof the third inverted amplifier A3. Then, the third inverted amplifiercircuit A3 outputs a first output signal (−(αVoc+βVo1), wherein α and βare positive constant numbers, respectively) to the first outputterminal OUT1 and outputs a second output signal (−γ(αVoc+βVo1), whereinα, β and γ are positive constant numbers, respectively).

Similarly, a signal proportional to the common-mode input signal Vic,which is an output signal of the non-inverted amplifier circuit A6, isadded to the output signal of the inverted amplifier A2 and the sum ofthe output signals of A2 and A6, Vo2, is inputted to the first (+) inputterminal of the fourth inverted amplifier A4.

Then, the fourth inverted amplifier circuit A4 outputs a third outputsignal (−(αVoc+βVo2) to the second output terminal OUT2, and outputs afourth signal (−γ(αVoc+βVo1), wherein α, β and γ are positive constantnumbers, respectively).

In the second embodiment, in the same manner as in the first embodiment,a gain for the differential signal path is represented by the product ofa gain of the inverted amplifier circuit A1 (A2) and a gain of theinverted amplifier circuit A3 (A4). In the case of a common-mode signal,an output signal of the inverted amplifier circuit A1 (A2) and an outputsignal of the non-inverted amplifier circuit A5 (A6) are added tothereby cancel the common-mode signal. Accordingly, a common-mode gaincan be decreased without increasing a number of internal nodes.

FIG. 7 shows an operational amplifier circuit in which invertedamplifier circuits A7 to A10 are added to the operational amplifiercircuit shown in FIG. 6 for decreasing common-mode gains of the invertedamplifier circuits A1 and A2 as explained with reference to FIG. 4.

According to this modification, although the first to sixth amplifiercircuits A1 to A6 are connected in the same manner as shown in FIG. 6,inverted amplifier circuits A7 to A10 are added. That is, the invertedamplifier circuit A7 is connected to the output terminal of the firstinverted amplifier circuit A1 and the inverted amplifier circuits A8 isconnected to the output terminal of the second inverted amplifiercircuits A2. The inverted amplifier circuits A9 and A10 are disposedbetween the output terminals of the first and second inverted amplifiercircuits A1 and A2. The inverted amplifier circuits A9 and A10 areconnected with each other in parallel with reverse polarity.

In the other words, a (+) input terminal of the inverted amplifiercircuit A9 is connected to the (−) output terminal of the invertedamplifier circuit A1. A (−) output terminal of the inverted amplifiercircuit A9 is connected to the (−) output terminal of the invertedamplifier circuit A2. A (+) input terminal of the inverted amplifiercircuit A10 is connected to the (−) output terminal of the invertedamplifier circuit A2. A (−) output terminal of the inverted amplifiercircuit A10 is connected to the (−) output terminal of the invertedamplifier circuit A1. Input and output terminals of the invertedamplifier circuit A7 are connected to the (−) output terminal of theinverted amplifier circuit A1. Input and ouput terminals of the invertedamplifier circuit A8 are connected to the (−) output terminal of theinverted amplifier circuit A2.

By this structure, in the same manner as in the operational amplifiercircuit shown in FIG. 4, the common-mode gain can be further decreasedwithout increasing the number of internal nodes.

Third Embodiment

FIG. 8 shows a balanced operational amplifier circuit according to athird embodiment of the present invention.

This operational amplifier circuit provides a first inverted amplifiercircuit A1 having a (+) input terminal that receives a first inputsignal IN1 and a second inverted amplifier circuit A2 having a (+) inputterminal that receives a second input signal IN2.

This operational amplifier circuit also provides a third invertedamplifier circuit A3 and a fourth inverted amplifier circuit A4. A (−)output terminal of the first inverted amplifier circuit A1 is connectedto a first (+) input terminal of the third inverted amplifier circuitA3. A(−) output terminal of the second inverted amplifier circuit A2 isconnected to a first (+) input terminal of the fourth inverted amplifiercircuit A4. A first(−) output terminal of the third inverted amplifiercircuit A3 is connected to a first output terminal OUT1. A first (−)output terminal of the fourth inverted amplifier circuit A4 is connectedto a second output terminal OUT2. Second (+) input terminals and second(−) input terminals of the third and fourth inverted amplifier circuitsA3 and A4 are connected with each other.

This operational amplifier circuit further provides a non-invertedamplifier circuit A11. A first (+) input terminal of the non-invertedamplifier circuit A11 is connected to the input terminal of the firstinverted amplifier circuits A1. A second (+) input terminal of thenon-inverted amplifier circuit A11 is connected to the input terminal ofthe second inverted amplifier circuits A2. A first (+) output terminalof the non-inverted amplifier circuit A11 is connected to the (−) outputterminal of the first inverted amplifier circuits A1. A second (+)output terminal of the non-inverted amplifier circuit A11 is connectedto the (−) output terminal of the second inverted amplifier circuits A2.

In the operational amplifier circuit shown in FIG. 8, when first andsecond input signals IN1 and IN2 are inputted to the first and secondinverted amplifier circuits A1 and A2 and the non-inverted amplifiercircuit A11, the first and second inverted amplifier circuits A1 and A2output an inverted output signal, respectively, and the non-invertedamplifier circuit A11 outputs signals proportional to the sum of thefirst and second input signals (IN1 and IN2). The sum signal (IN1+IN2)is added to the inverted output signal of each of the first and secondinverted amplifier circuits A1 and A2. The added signals are Vo1 andVo2. The added signals Vo1 and Vo2 are inputted to the third and fourthinverted amplifier circuits A3 and A4, respectively.

Thus, the third inverted amplifier circuit A3 outputs a first outputsignal (−(αVoc+βVo1)) to the first output terminal OUT1 and a secondoutput signal (−γ(αVoc+βVo1)). On the other hand, the fourth invertedamplifier circuit A4 outputs a third output signal (−(αVoc+βVo2)) to thesecond output terminal OUT2 and a fourth output signal (−γ(αVoc+βVo2)).The estimated common-mode output signal Voc is generated by adding thesecond output signal and the fourth output signal.

The circuit structure shown in FIG. 8 exemplifies that the non-invertedamplifier circuit A11 generates a common-mode input signal from thefirst and second input signals IN1 and IN2. This may be used in caseswhere no common-mode input signal is available in the circuit structureshown in FIG. 6.

This non-inverted amplifier circuit A11 is constituted by amulti-input/multi-output amplifier circuit and is constituted, forexample, by inverted amplifier circuits Ab1 to Ab5 as shown in FIG. 9.

In detail, output terminals of the inverted amplifiers Ab1 and Ab2 areconnected with each other and connected to an input terminal of theinverted amplifier Ab3. Input and output terminals of the invertedamplifier Ab3 are connected with each other and connected to inputterminals of the inverted amplifiers Ab4 and Ab5.

According to this circuit structure, common-mode signals from theinverted amplifiers Ab1 and Ab2 are added and then inputted to theinverted amplifiers Ab4 and Ab5 via the inverted amplifier Ab3. Theinverted amplifier Ab4 and Ab5 output signals proportional to the sum ofthe input signals IN1 and IN2.

FIG. 10 shows an embodiment in which inverted amplifier circuits A7 toA10 are added to the operational amplifier circuit shown in FIG. 8 tofurther decrease the common-mode gain as explained with reference toFIG. 4.

According to this modification, although the first to sixth amplifiercircuits A1 to A6 are connected in the same manner as shown in FIG. 8,inverted amplifier circuits A7 to A10 are added. That is, the invertedamplifier circuit A7 is connected to the output terminal of the firstinverted amplifier circuit A1 and the inverted amplifier circuits A8 isconnected to the output terminal of the second inverted amplifiercircuits A2. The inverted amplifier circuits A9 and A10 are disposedbetween the output terminals of the first and second inverted amplifiercircuits A1 and A2. The inverted amplifier circuits A9 and A10 areconnected with each other in parallel with reverse polarity.

By this structure, in the same manner as in the operational amplifiercircuit shown in FIG. 4, the common-mode gain can be further decreasedwithout increasing the number of internal nodes.

FIG. 11 shows an operational amplifier circuit to which both the firstembodiment and the third embodiment are applied. In detail, theamplifier circuits A1 to A10 correspond to the amplifier circuits A1 toA10 of the first embodiment shown in FIG. 4. The amplifier circuit A11in FIG. 11 corresponds to the amplifier circuit A11 of the thirdembodiment shown in FIG. 8. With this structure, the common-mode gainalso can be further decreased without increasing the number of internalnodes in each circuit path of the differential signals.

FIG. 12 shows a circuit diagram in which the operational amplifiercircuit shown in FIG. 11 is constituted by MOS transistors. Thetransistor MN1 corresponds to the inverted amplifier circuit A1, and thetransistor MN2 corresponds to the inverted amplifier circuit A2. Thetransistors MN11-1, MN11-2, MP11-1 to MP11-3 constitute the non-invertedamplifier circuit A11. The transistors NM7 to MN10 correspond to theinverted amplifier circuits A7 to A10, respectively.

The transistors MN5, MP5, MP5-1 and MP5-2 constitute the non-invertedamplifier circuit A5, and the transistors MN5, MP5, MP6-1 and MP6-2constitute the non-inverted amplifier circuit A6. The input portion ofthe non-inverted amplifier circuits A5 and A6 shares the transistors MN5and MP5.

The transistors MN3-1 to MN3-4 and MP3-1 to MP3-4 constitute theinverted amplifier circuit A3 and the transistors MN4-1 to MN4-4 andMP4-1 to MP4-4 constitute the inverted amplifier circuit A4.

As will be understood from the transistor circuit shown in FIG. 12, thisoperational amplifier circuit can be realized by a structure having nostacked-transistor connection, resulting in a low power-supply voltageoperation.

Furthermore, as explained above, in the path from the input IN1 to theoutput OUT1, also in the path from the input IN2 to the output OUT2, itis possible to limit the number of internal nodes to one. That enablesan improvement in the frequency characteristic for a differentialsignal.

FIGS. 13 and 14 show a sample/hold circuit using an operationalamplifier circuit Amp1 according to the present invention. In thissample/hold circuit, at the time of sampling, as shown in FIG. 13, theswitches SW1 to SW6 are closed and the switches SW7 to SW10 are opened.An input signal IN1 is provided to a capacitor C1, which is grounded viaSW3. A first input terminal and a first output terminal of Amp1 areconnected via SW5. In the same manner, an input signal IN2 is providedto a capacitor C2, which is grounded via SW4. A second input terminaland a second output terminal of Amp1 are connected via SW6.

In this state, when the input signals IN1 and IN2 are inputted, theinput signals are stored in the capacitors C1 and C2. In other words,the input signals are memorized (sampled).

At the time of reading, as shown in FIG. 14, the switches SW1 to SW6 areopened and the switches SW7 to SW10 are closed. The first input terminaland the first output terminal of Amp1 are connected through SW7, C1 andSW9. The second input terminal and the second output terminal of Aniplare connected through SW8, C2 and SW10. At this time, the signals storedin the capacitors C1 and C2 are outputted to the operational amplifiercircuits OPA.

In the sample/ hold circuit as mentioned above, MOS transistorsconstitute the switches in general. In an MOS transistors, at the timeof turning on and off, channel charge is absorbed and released incommon-mode. Assuming that the switches are composed of NMOStransistors, when the switches SW1 and Sw2 are turned off, the voltagesat the input terminals of the Amp1 increase in common-mode due to thischannel charge injection to the capacitors C1 and C2. If this voltageincrease is not prevented, an amplification operation is saturated. Inthe present invention, since common-mode components are canceled in theoperational amplifier circuit OPA, the common-mode gain decreases,resulting in no saturation. A low power-supply voltage operation of asample/hold circuit can be achieved.

FIG. 15 shows a filter using an operational amplifier circuit accordingto the present invention. A filter is constituted by integrators. Anintegrator is composed of an amplifier Amp1, resistors R1 to R4 andcapacitors C1 and C2. According to the present invention, an operationalamplifier circuit of the present invention is used as the amplifierAmp1.

The filter is constituted, for example, by integrators Int1 to Int5. Afirst stage integrator Int1 uses the operational amplifier circuit forgenerating a common-mode signal as shown in FIGS. 1 and 8. Operationalamplifier circuits used in integrators Int2 to Int5 at the subsequentstages can utilize the common-mode components Voc contained in theoutput signal of the operational amplifier circuit at the precedingstages, and therefore employ operational amplifier circuits shown inFIGS. 6 and 7.

As explained above, according to an operational amplifier circuit of thepresent invention, in an operational amplifier circuit of a balancedstructure having two gain stages which is appropriate for a lowerpower-supply voltage, the frequency characteristic can be improved bysuppressing the common-mode signal sufficiently and limiting the numberof internal nodes in each differential signal path to one.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details, representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1. An operational amplifier circuit, comprising: a first invertedamplifier circuit that receives a first input signal; a second invertedamplifier circuit that receives a second input signal; a firstnon-inverted amplifier circuit that receives a common-mode input signal,a second non-inverted amplifier circuit that receives the common-modeinput signal, a third inverted amplifier circuit that receives anestimated common-mode output signal and a sum of the output signal ofthe first non-inverted amplifier and the output signal of the firstinverted amplifier circuit, and outputs a first output signal and asecond output signal; and a fourth inverted amplifier circuit thatreceives the estimated common-mode output signal and a sum of the outputsignal of the second non-inverted amplifier and the output signal of thesecond inverted amplifier circuit, and outputs a third output signal anda fourth output signal, wherein adding the second output signal and thefourth output signal creates the estimated common-mode output signal. 2.The operational amplifier circuit according to claim 1, wherein thefirst and second input signals are differential input signals.
 3. Theoperational amplifier circuit according to claim 1, further comprising:a fifth inverted amplifier circuit that receives the output signal ofthe first inverted amplifier circuit and outputs an output signal fedback to the output of the first inverted amplifier circuit; a sixthinverted amplifier that receives the output signal of the secondinverted amplifier circuit and outputs an output signal fed back to theoutput of the second inverted amplifier circuit; a seventh invertedamplifier circuit that receives the output signal of the first invertedamplifier circuit and outputs an output signal fed back to the output ofthe second inverted amplifier circuit; and an eighth inverted amplifierthat receives the output signal of the second inverted amplifier circuitand outputs an output signal fed back to the output of the firstinverted amplifier circuit.